1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device provided with a timing-stabilization circuit.
2. Description of the Related Art
Semiconductor devices such as SDRAMs (synchronous dynamic random access memories), which operate in synchronism with synchronization signals, require stabilization of a data-access time and a data-hold time with respect to the synchronization signals in order to achieve a higher operation speed. To meet this demand, a timing-stabilization circuit such as a DLL (delay-locked loop) circuit is provided so as to stabilize timings of internal clock signals used for data input/output.
FIG. 1 is a block diagram of a circuit which adjusts a data-output timing based on a DLL circuit.
The circuit of FIG. 1 includes an input circuit 501, a variable-delay circuit 502, an output circuit 503, a phase comparator 504, a delay-control circuit 505, a dummy-variable-delay circuit 506, a dummy-output circuit 507, and a dummy-input circuit 508.
A clock signal CLK input to the input circuit 501 is compared with a reference voltage level, and is output from the input circuit 501 as a clock signal c-clk. The clock signal c-clk is then delayed by the variable-delay circuit 502 by an appropriate delay amount, and is supplied to the output circuit 503. The output circuit 503 uses the supplied internal-clock signal as a synchronization signal for latching data DATA which is to be output from the device. The latched data DATA is then supplied from the output circuit 503 to an exterior of the semiconductor device as data DQ.
The signal path from an input node of the clock signal CLK to the output circuit 503 inevitably introduces a delay which is inherent to the circuit, so that the data DQ output to the exterior of the device has a timing displacement relative to the clock signal CLK. In order to ensure that the data DQ output from the output circuit 503 is adjusted to have a predetermined timing relation with the externally provided clock signal CLK, a DLL circuit mainly comprised of the phase comparator 504, the delay-control circuit 505, and the dummy-variable-delay circuit 506 is employed.
The clock signal c-clk is further supplied to the dummy-variable-delay circuit 506. The dummy-variable-delay circuit 506 is controlled to delay the clock signal c-clk by the same delay amount as that applied by the variable-delay circuit 502. The delayed-clock signal output from the dummy-variable-delay circuit 506 is then supplied to the dummy-output circuit 507, which emulates the output circuit 503. The clock signal output from the dummy-output circuit 507 is supplied as a dummy-clock signal d-i-clk to the phase comparator 504 via the dummy-input circuit 508, which has the same delay characteristics as the input circuit 501.
The phase comparator 504 makes a comparison of the clock signal c-clk with the dummy-clock signal d-i-clk in terms of their phases. To ensure that both clock signals have the same phase, the phase comparator 504 controls the delay amount of the dummy-variable-delay circuit 506 via the delay-control circuit 505. In this manner, the clock signal output from the dummy-output circuit 507 is adjusted so as to have a predetermined timing relation with the input clock signal CLK.
A total delay of the variable-delay circuit 502 and the output circuit 503 is equal to a total delay of the dummy-variable-delay circuit 506 and the dummy-output circuit 507. Because of this, when the clock signal output from the dummy-output circuit 507 has the predetermined timing relation with the input clock signal CLK, the data DQ output from the output circuit 503 to the exterior of the device ends up having the same predetermined timing relation with the input clock signal CLK.
In this configuration, even when the characteristics of the input circuit 501, the variable-delay circuit 502, and the output circuit 503 are changed due to variations in a power voltage and/or temperature, the characteristics of the dummy-input circuit 508, the dummy-variable-delay circuit 506, and the dummy-output circuit 507 also change in the same manner. Because of this, the data DQ output from the output circuit 503 to the exterior of the device always keeps the same timing relation with the input clock signal CLK regardless of a power-voltage variation and/or a temperature variation.
Each of the variable-delay circuit 502 and the dummy-variable-delay circuit 506 is comprised of a plurality of delay elements connected in series. When a signal is input to a first stage of the delay elements and output from a last stage of the delay elements, a signal delay commensurate with the number of delay elements from the first stage to the last stage is introduced to the signal. When a signal is input to n-th stage of the delay elements and output from the last stage, the signal is delayed by a delay length commensurate with the number of delay elements from the n-th stage to the last stage. In this manner, a delay of the output signal can be adjusted by controlling which stage of the delay elements receives the input signal. If an entry point of the input signal is shifted by one stage toward the last stage, a delay of the output signal is increased by a delay length corresponding to one stage of delay elements.
Where the clock signal c-clk and the dummy-clock signal d-i-clk are adjusted to have a 360.degree.-phase difference, for example, a delay amount of the variable-delay circuit 502 and the dummy-variable-delay circuit 506 is shifted step by step until the 360.degree.-phase difference is achieved (i.e., until the DLL circuit locks on). In normal active conditions of the semiconductor device, a clock cycle has a relatively small fluctuation despite a presence of variations in a power voltage and/or temperature. Because of this, the step-wise adjustment of the delay amount can cope with the fluctuation of the clock cycle.
At the time of power on, however, the variable-delay circuits are first reset to the initial state, and, then, a phase adjustment of the clock signal commences from an initial delay amount. In this case, therefore, the step-wise adjustment of the delay amount needs a lengthy time period before the DLL circuit locks on.
In a standby mode where a clock-signal frequency and/or a power voltage are lowered with an aim of reducing power consumption, the delay amount of the variable-delay circuits is quite different from that used in the normal active conditions of the device. Because of this, when the semiconductor device returns from the standby mode to the normal mode, a phase adjustment takes a lengthy time before the variable-delay circuits lock on.
Accordingly, there is a need for a semiconductor device which can reduce a time period required for a phase adjustment before a timing-stabilization circuit locks on.